1. Field of the Invention
This invention is related to the field of systems including processors and peripheral devices, and managing power consumption in such systems.
2. Description of the Related Art
As the number of transistors included on an integrated circuit “chip” continues to increase, power management in the integrated circuits continues to increase in importance. Power management can be critical to integrated circuits that are included in mobile devices such as personal digital assistants (PDAs), cell phones, smart phones, laptop computers, net top computers, etc. These mobile devices often rely on battery power, and reducing power consumption in the integrated circuits can increase the life of the battery. Additionally, reducing power consumption can reduce the heat generated by the integrated circuit, which can reduce cooling requirements in the device that includes the integrated circuit (whether or not it is relying on battery power).
Clock gating is often used to reduce dynamic power consumption in an integrated circuit, disabling the clock to idle circuitry and thus preventing switching in the idle circuitry. Additionally, some integrated circuits have implemented power gating to reduce static power consumption (e.g. consumption due to leakage currents). With power gating, the power to ground path of the idle circuitry is interrupted, reducing the leakage current to near zero.
Clock gating and power gating can be effective power conservation mechanisms. However, in some cases, these mechanisms are not as effective as desired. For example, systems that include processors can cause the processors to enter a sleep state to conserve power. While the processor is in the sleep state, other components in the system are still active, and often are operating at performance levels that support the active processors. When the processors are in the sleep state, these other components need not be operating at such a high performance level. Similarly, when the processors are awakened from the sleep state, the performance level at which the processors and other components need to operate to support the activities being performed by the system may be different than the performance level prior to the processor entering the sleep state.
The sleep/wake transitions of the processors and other components are changed under software control. The software executes on the processors, and thus changing the performance levels of the processors and other components can affect the amount of time required to execute the software. These effects impact the efficiency of the transition, impacting the power conserved and the performance of the application. Furthermore, the software execution time can affect how often the processor is transitioned to the sleep state, and the amount of reduced performance that can be tolerated in the rest of the system.